It is common in semiconductor devices to make a vertical contact between two horizontal conductive layers by etching a hole (sometime called a "via") in the dielectric that separates the two layers. Such a contact can be established in a number of ways. The traditional way of forming a contact has been to etch a via in the dielectric that covers a first conductive layer, and then depositing a second conductive layer on the dielectric layer such that the material that comprises the second conductive layer enters the via and makes mechanical/electrical contact with the first conductive layer. Alternatively, the trend in more modern devices has been to etch the via, and then to fill the via with a conductive substance to form a "plug." A plug is formed by depositing the conductive substance in the via so as to come in mechanical/electrical contact with the first conductive layer, and then polishing the remainder of the conductive substance which resides on top of the dielectric surface away, for example, by chemical-mechanical-polishing (CMP). Once the plug is formed, the second conductive layer can be deposited on top of the plug so as to come in mechanical/electrical contact with the plug, and thus in mechanical/electrical contact with the first conductive layer.
The various ways of making contacts have certain drawbacks. For example, in DRAM (dynamic random access memory) technologies it is desirable to make periodic contacts to the cell plate of the capacitor in each cell for the purpose of applying a reference voltage thereto. (An example of a DRAM cell with a cell plate can be found in the assignee's copending application Ser. No. 09/385,586, which is herein incorporated by reference in its entirety). To economize the process, this processing step can also be used to form contacts to other structures, for example, to the control gates in the peripheral portion of the memory device. However, the mechanical/electrical quality of the contacts formed can vary due to the fact that the dielectric overlying the control gate and the cell plate are of different thicknesses, and due to the fact the control gate and the cell plate are made from different materials which will be more or less susceptible to the via etch. These problems are worsened if the conductive materials to be brought into contact do not adhere well to one another (e.g., tungsten and polysilicon). Moreover, the CMP polishing can cause the material in the via that forms the plug to become loose, thereby rendering the contact mechanically/electrically unstable. The cell plate vias are particularly susceptible to this sort of instability because they are thin in comparison to the control gate vias. (Other problems associated with making a reliable cell plate contact, and a method for fixing such problems, can be found in the assignee's copending application Ser. No. 09/385,586 (Micron #99-0196)).
Special problems with contact stability are exacerbated when it is desired to electrically connect not two but three or more horizontal conductive layers. The traditional approach has been to create vias to connect each conductive layer to only the conductive layer directly above it. However, this technique is labor intensive and is susceptible to problems when the vias are stacked on top of one another due to the potentially uneven surface of the conductor underlying a given via. Misalignment of the vias with respect to one another can exacerbate the unreliability of the contact.
The present inventions provide a contact structure that fixes these problems, and a method of producing such structures, thereby providing a relatively simple and reliable way for creating quality contacts between conductive layers.